1. Field of the Invention
The present invention is generally directed to a method and system for optimizing migrated implementation of a system design. In certain applications, the present invention is directed to a method and system of reading in a circuit schematic or layout for a first circuit design of a first technology node (e.g. 45 nm), abstracting a hierarchical representation into a tree structure, reading in a target integrated circuit schematic of a circuit of a second technology node (e.g. 32 nm) being related to the source schematic or layout file, abstracting out the hierarchical structure of it, and assessing the most optimized migration steps to transform the source schematic or layout to the target layout.
2. Description of the Related Art
In integrated circuit (IC) design, it is often desirable to reuse existing circuit designs, even when transitioning from one generation or node of technology to another. No tools presently exist to accurately and efficiently migrate or transform a hierarchical structure representation, source layout, or a source schematic of an integrated circuit file from a first technology generation or node (e.g. 45 nm) to a second technology generation or node (e.g. 32 nm) in a sufficiently automated manner.
Layout migration or transformation from one technology node (e.g. 45 nm) to another (e.g. 32 nm) is difficult when the source and target schematic have mismatches in name or structure. Typically, an integrated circuit designer would need to manually intervene on every piece of mismatched data to be migrated and must laboriously create a table of ‘from’ and ‘to’ cell names so that the migration tool knows what to do. When there are discrepancies, such as a new cell being added in the design hierarchy, the addition must be done manually. Performing these manual interventions increases the required design time, resources, and costs.
In electronic design automation (EDA), and specifically migration/transformation of schematics/layouts from one technology node to another, such a migration requires extensive manual intervention from skilled design engineers. A common goal is to reuse the already-created source schematic and source layout files, but designers are forced to manually create a cell naming table, manually specifying ‘from’ and ‘to’ values, and manually fixing design structure changes, including manual addition of devices, layers of hierarchy, etc.
This approach is not very practical as many errors are often made and migration problems may often arise. Unfortunately, no automated tool is available to effectively aid in this migration process.
The current practice of rendering a source schematic or layout design and a manually created table of ‘to’ and ‘from’ values with manual fixing of structural changes is an inefficient, error prone, and labor-intensive manner of performing such a migration or transformation.
Further still, the resulting target layout file will not be in an Layout Versus Schematic (LVS) clean or formally verified, signed off condition and the entire process of verification, layout versus schematic verification, design rule checks (DRC), electrical rule checks (ERC), and the entirety of the formal verification process may well need to be repeated on this new target layout file. This adds substantial delay and cost to such a migration. If problems are found during this formal design verification, the designers will have to go back, modify designs, and iterate through this entire formal verification process over and over again, thereby compounding the inefficiency of the present approach. Consequently, time delays, budget overruns, and inefficiencies are introduced into the overall manufacturing and migration process.
There is therefore a need for a method and system for automatically reconciling hierarchies with automated solution sets and/or optimizing migrated implementation of a system design that does not depend on manual human intervention and to/from table lookup creation with individual element structural changes being fixed.